In flip chip processing of integrated circuit (IC) chips, controlled collapse chip connection (C4) solder bumps are typically used to connect IC dies to packaging. However, due to the coefficient of thermal expansion (CTE) mismatch between different layers in the packaging, C4 solder bumps can experience large stresses which can lead to crack formation during chip joining. These CTE mismatches must be managed, especially in lead free (Pb-free) solder bumps, to control cracking during chip joining (referred to as “white bump formation”).
Redistribution layers (RDL) are commonly used as top-level wiring on an integrated circuit (IC) for the purpose of redistributing chip-level I/O and power, and for customizing or adding/eliminating connections needed for particular chip-to-package product configurations.
RDL's are typically formed by adding a layer of insulating dielectric material onto a finished back-end-of-line (BEOL) structure at wafer level, and then forming the new level of redistribution wiring either in aluminum or copper metalization using standard BEOL processing. Once the metalized redistribution layer is patterned, this new RDL wiring level is coated with a layer of insulating organic dielectric material through which the interconnect openings for solder pad/bump connections are formed. In a particular type of RDL, the first insulating dielectric material in which the wiring is formed may be an organic polymer (e.g. BCB or PSPI).
As solder bump size decreases into the 75 micrometer range, effective current distribution becomes more important in order to meet C4 bump-level electromigration requirements, and the thick Cu structure provides a mechanism for achieving enhanced current distribution in the manner of a copper pillar or partial copper pillar structure.